Content addressable memory (CAM) is a type of computer memory utilized in high speed searching applications. Most CAM devices utilize static random access memory (SRAM) as data storage devices (utilizing transistors to store memory), and additional transistors and complementary transistors for match operations. Often in these CAM devices search-line access elements and word-line access elements are necessary to operate and program individual memory cells in the memory arrays. These search-line access elements and word-line access elements are often comprised of power intensive large drive field effect transistors (FET).
Content Addressable Memory (CAM) devices are used in applications requiring matching operation on bit patterns, such as table lookup applications used by routing and switching systems in computer network applications. Typically, CAM devices provide for the direct comparison of stored data entries with a supplied value to be compared, called a comparand, in a single access. In contrast, when using conventional Random Access Memory (RAM) for the same search operation, stored data entries are compared by supplying the address of each of the stored data entries to the RAM device, retrieving each of the data entries stored at each of the addresses, and passing the data to an arithmetic logic unit (ALU), where it is then compared to the comparand. CAM devices, on the other hand, allow the comparand to be directly compared with all the stored data entries simultaneously, and any stored data entries matching the input entry generate a match signal. More specifically, each bit position of the comparand is compared with the corresponding bit positions of data entries stored in the CAM device. A priority encoder in the CAM device identifies which matching data entry is output first in the case of multiple matching data entries, with this data entry being termed the highest priority match, as will be explained later in this document.
A conventional Ternary Content Addressable Memory (TCAM) cell can store three states, including a logic “0”, logic “1” and a “don't care”. TCAM function includes writing data to storage cell in write operation, comparing input data with memory content (all data in storage cell) and outputting the address of identical (matching) content in search operation. The “X” bit means always match. There are 3 kinds of data for 1 bit, “0”, “1” and “X” (don't care). A TCAM is grouped into several array segments, and each segment contains an array of TCAM cell pairs. Each TCAM cell pair is a bit and contains a storage cell and a don't-care cell. The storage value of each bit may be a “0” state, an “1” state or an “X” state that is also called don't-care state. One terminal of the storage cell connects to an electrical power source for receiving a voltage, and the other terminal connects to the ground for discharging.
A conventional TCAM cell structure is for example 16 T & 12 T SRAM-based TCAM which includes storage part (6 T or 4 T SRAM) and compare part (nand or nor logic). Please refer to “A ternary content-addressable memory (TCAM) based on 4 T static storage and including a current-race sensing scheme”, JSSC, 2003.
A TCAM may be in read operation, write operation and search operation or standby mode. And, it is not necessary to compare the storage data of a bit with the inquiry data when “X” state is set. In conventional TCAM cell, write operation is similar with that of SRAM, described as below table. In search operation of TCAM cell, search-data pair and storage-data pair connect to compare logic (nand or nor) which will discharge matching line (ML) if search-data pair is different from storage-data pair.
Data(SRAM1, SRAM2)0(1, 0)1(0, 1)X(0, 0)
The storage cell still connects to between the electrical power source and the ground via a charging terminal and a discharging terminal, respectively, and that will be accompanied by a leakage current. The leakage current consumes the electrical power and furthermore decreases the device reliability, so the leakage current must be reduced to as small as possible. Moreover, read disturb probably happen when large voltage stress on non-volatile memory (NVM) or large current thru NVM.
The time needed to discharge the match line varies depending on the number of mismatched cells. To minimize the discharge speed variation, larger sized transistors are needed. This, however, results in larger size TCAM cells. Therefore, a discharge speed difference also negatively affects the density of a TCAM.
Accordingly, the technique of reducing the leakage current and read disturb for TCAM has been developed. In view of the foregoing, a need exists for a content addressable memory cell that is stably operable at low operation voltage, low power consumption, and facilitates manufacture of a high density CAM. Thus, the invention's scheme and method are proposed.